CDC

A clock domain crossing occurs when a digital signal moves from one part of a circuit that runs on one clock frequency to another part running on a different clock frequency, or from an asynchronous source into a synchronous system. In practice, this means a signal generated and used within one timing domain must somehow enter and be safely used in another. The problem is that the receiving clock may sample the incoming signal at an unlucky moment, catching it mid-transition, which causes metastability: the receiving flip-flop enters an undefined state between 0 and 1, potentially corrupting data downstream.

Metastability is not a minor glitch. When a flip-flop enters a metastable state, it can take an unpredictable time to resolve to a valid logic level, and sometimes it never fully settles before the next clock edge samples it again. This cascades into logic errors, timing violations, and system failure. For this reason, crossing clock domains is one of the most dangerous operations in digital design. A design that passes simulation may fail silently in the field because metastability is probabilistic: it might occur rarely, but given enough clock cycles, it will occur.

Synchronization strategies

The standard solution is a synchronizer: a chain of two or more flip-flops clocked by the destination domain, with the incoming signal applied to the first flip-flop. Even if the first flip-flop goes metastable, the second flip-flop has time to see a stable output and samples it cleanly. For single-bit control signals, a two-stage synchronizer is often sufficient. Multi-bit data crossing requires more complex structures, such as Gray code counters or handshake protocols, because multiple bits cannot be synchronized together without risk of skew between bits.

Clock domain crossing is common in real systems. A chip may have multiple internal clock domains for power management, or external asynchronous signals (reset buttons, sensor inputs, received data) must be synchronized to an internal clock. FPGAs and ASICs handling high-speed interfaces frequently cross between the interface clock and a system clock. Failure to handle CDC properly is a leading source of subtle, hard-to-debug silicon bugs, which is why formal verification of CDC is increasingly standard practice in professional design flows.