clock skew
A phenomenon in synchronous digital circuit systems in which the same sourced clock signal arrives at different components at different times due to gate or wire signal propagation delay.
clock skew: when your clock signal shows up late to the party
Clock skew is the difference in arrival time of the same clock signal at different points in a digital circuit. In synchronous systems, all logic gates are supposed to change state on the same clock edge. When that clock edge reaches one part of the circuit before another, the circuit violates its own timing contract, and logic errors follow. The delay accumulates through the wiring and through logic gates themselves as the signal propagates from the clock source to distant registers.
Skew arises from two sources: propagation delay through the metal traces and vias on a printed circuit board or integrated circuit, and propagation delay through buffering logic gates inserted along the clock distribution tree. A microprocessor running at 3 GHz has a clock period of roughly 0.33 nanoseconds. Even a propagation delay of 0.1 nanoseconds across a board or chip creates measurable skew. In large systems, unmanaged skew can eat into setup and hold time margins, the tiny windows in which data must be stable relative to the clock edge.
Measurement and management
Designers measure skew as the maximum time difference between the earliest and latest arrival of a clock signal at its destination flip-flops or latches. Typical tolerance budgets for modern logic range from 10 to 30 percent of the clock period. To control skew, engineers use matched-length clock distribution networks, balanced clock trees, and specialized low-skew clock buffer circuits. Some systems employ a phase-locked loop (PLL) at each region of the chip to regenerate and re-synchronize the clock locally, converting a global skew problem into smaller local ones.
Negative skew, where a downstream register receives the clock earlier than intended, can be as problematic as positive skew. It compresses the time available for data to settle after the previous clock edge, creating setup time violations. Conversely, excessive positive skew can create hold time violations if data changes too quickly after an earlier clock arrival elsewhere in the system.
In integrated circuits, skew is now a dominant design challenge. Modern process nodes at 5 nm and below see such high clock frequencies and such tight timing margins that even nanometer-scale variations in metal thickness or doping concentration create measurable skew. Foundries and design teams now characterize skew corner cases and include skew budgeting in static timing analysis from the earliest stages of layout.