DLL

A delay-locked loop is a feedback circuit that measures the phase difference between a reference clock and a delayed copy of itself, then adjusts that delay until the two signals align. Unlike a phase-locked loop, which multiplies frequency, a DLL keeps the output frequency identical to the input while correcting the phase lag that accumulates through signal routing and logic gates. The circuit continuously samples both signals and drives a voltage or current control element (a delay line made of inverters or other logic stages) to minimize skew.

DLLs are foundational in synchronous memory interfaces. In DRAM and GDDR chips, the DLL aligns the internal clock grid to the external clock edge, ensuring that data is sampled and output at precise moments. Without DLL correction, the natural delay through silicon from the pad to the core would cause timing failures. A typical DLL must lock within a few hundred clock cycles on power-up and track drift caused by temperature swings and supply voltage sag across the chip.

Locking behavior and bandwidth

The DLL loop has a characteristic lock time and settling behavior. A slow loop has low bandwidth and tracks slowly but rejects high-frequency noise well. A fast loop locks quickly but can overshoot or ring. Most production DLLs use a proportional-integral control law to balance speed and stability. The delay line itself is the critical component: it must have fine granularity (small steps between delay levels), low sensitivity to voltage and temperature variation, and enough total delay range to cover process spread and power supply transients.

Common failure modes include: false lock, where the DLL locks to a harmonic or subharmonic of the input clock and appears stable but is actually phase-shifted by a multiple of the clock period; lock loss, when temperature or supply voltage changes exceed the loop's tracking bandwidth; and deadlock, where the loop cannot reach equilibrium and oscillates. DLL designs often include lock detectors that verify the phase error is small before declaring lock valid.

DLLs differ from phase-locked loops chiefly in their voltage-controlled delay element rather than a voltage-controlled oscillator. This makes them simpler to integrate, faster to lock, and more tolerant of supply noise, since they have no frequency generation to destabilize. They are standard in high-speed DRAM, DDR interfaces, and synchronous SRAMs, and are also used in programmable logic devices and ASICs to distribute clocks with minimal skew across large tiles.