floor plan

A floor plan in integrated circuit design is the physical arrangement of functional blocks, logic cells, memory arrays, power distribution networks, and interconnect on a silicon die. It translates the logical schematic into a concrete geometry that fabricators can manufacture. Before any transistor gets placed or any metal layer gets drawn, the floor plan determines how much area the chip will consume, how signals will travel between blocks, and whether the design can meet timing, power, and thermal constraints.

The floor plan drives multiple downstream decisions. Block placement affects wirelength: putting a datapath far from memory increases capacitance and signal delay. It governs thermal hotspots by concentrating high-power logic in one region, which can cause localized overheating and reliability problems. The plan also must account for power delivery; current has to flow from pad to every block without excessive voltage drop, so the position and size of supply rails matter physically. I/O pads sit around the chip perimeter, so blocks that communicate with off-chip must be placed accordingly to minimize routing congestion.

Variants and practical workflow

Smaller chips may use a single monolithic floor plan where all logic sits at one hierarchical level. Large systems-on-chip use hierarchical floor planning: a top-level plan divides the die into major regions (CPU cluster, GPU cluster, memory controllers, security subsystems), and each region gets its own internal floor plan. This containment strategy helps teams work in parallel and isolates the effects of local routing congestion.

The floor plan is iterative. Initial placement is often done by automated tools using metrics like half-perimeter wirelength or simulated annealing, but designers refine it based on timing reports, power analysis, and physical design rules. A block might be widened and shortened to reduce wirelength to a critical neighbor, or rotated to align with power straps. When the design reaches detailed routing (placement and routing, or P and R), the floor plan becomes fixed; moving a block at that stage means ripping up thousands of routed nets.

Common problems stem from poor floor planning. Undersizing a block forces overly dense placement of cells inside it, raising local congestion and making routing impossible. Oversizing wastes die area and increases cost per chip. Isolating blocks without careful attention to signal paths creates long interconnect runs that violate timing constraints. The name itself is borrowed from architecture: just as a building floor plan shows where rooms go, a chip floor plan shows where functional units go on the silicon real estate.