PLIC

A PLIC is a hardware component in RISC-V systems that sits between interrupt sources (peripherals, timers, external devices) and the processor cores (called harts in RISC-V terminology). Its job is straightforward: when a device needs attention, the PLIC receives the signal, decides which hart should handle it, and delivers the interrupt. Without a PLIC, each hart would need direct connections to every interrupt source, which becomes unmanageable in systems with many cores and many devices.

The PLIC manages interrupts by assigning each source a priority level, typically ranging from 0 to 15 or higher depending on the implementation. It also supports threshold registers: each hart can set a threshold value, meaning it will only accept interrupts with priority above that threshold. This allows a core to defer low-priority work temporarily or reject entire classes of interrupts during critical sections. The PLIC tracks which interrupts are pending, which are enabled, and which hart should service each one.

Routing and Hart Selection

The PLIC can route a single interrupt source to multiple harts or to specific harts only. In some designs, an interrupt is claimed by the first hart that reads the PLIC's claim register; in others, the PLIC itself selects the target hart. The selection logic considers priority, threshold, and sometimes load balancing. Once a hart claims an interrupt, it must complete handling and then write a completion register to signal the PLIC that it is done. This allows the PLIC to deassert the interrupt and potentially send it to another hart if needed.

PLIC implementations vary. Simple designs are hardwired with a fixed number of interrupt sources and harts; complex systems include configurable contexts (a hart may have separate M-mode and S-mode contexts, each with its own threshold and claim registers). The PLIC itself is usually memory-mapped, occupying a contiguous address range that software accesses via load and store instructions. Typical implementations allocate roughly 4 bytes per interrupt source plus 8 bytes per hart context, so memory footprint grows with scale.

In practice, problems arise when interrupt priorities are misconfigured, causing latency-sensitive devices to be starved by lower-priority sources, or when the threshold is set too high, causing interrupts to be lost. The PLIC's role makes it invisible during normal operation but critical during system integration. Debugging often requires examining the memory-mapped registers directly to see which interrupts are pending or enable, and which hart contexts have claimed them.