XNOR gate

An XNOR gate is a digital logic gate that outputs a high signal (logic 1) when both its inputs are identical, and outputs low (logic 0) when they differ. With two inputs A and B, the gate produces a true result only when A and B match, whether both are 1 or both are 0. This complementary behavior to XOR is why it is sometimes called an equivalence gate or XNOR gate, the negation of exclusive OR.

The XNOR function is expressed in Boolean algebra as the output Q equals (A AND B) OR (NOT A AND NOT B). This can also be written as Q equals A XNOR B, or as the logical equivalence A if and only if B. In practice, many implementations combine an XOR gate with a NOT gate (inverter), though dedicated XNOR cells in modern logic libraries are optimized as single gates rather than composite structures.

Construction and Implementation

XNOR gates are fabricated in silicon using CMOS (complementary metal-oxide-semiconductor) technology, or in older designs as TTL (transistor-transistor logic). A basic CMOS XNOR requires a pull-up network and pull-down network configured to produce the equivalence function. Most standard-cell libraries offer XNOR gates with 2, 3, or 4 inputs, though two-input versions are the most common. Fan-out and propagation delay vary by process node; a typical 2-input XNOR in a 28 nm process exhibits propagation delay around 10 to 15 picoseconds.

XNOR gates are essential in comparator circuits, parity checkers, and magnitude comparison operations. They appear frequently in arithmetic units where equality testing is needed, in error detection logic, and in control systems that need to verify matching signals. In microcontroller and FPGA designs, XNOR operations are often synthesized from simpler primitives rather than instantiated as discrete cells, depending on the target architecture and optimization goals.

One common pitfall is confusing XNOR behavior with the AND gate in circuit design. Where AND requires both inputs high, XNOR outputs high for any matching pair of inputs. This distinction becomes critical in applications like comparator design, where incorrect gate selection will silently produce wrong results under certain input conditions rather than failing obviously.