adder-subtractor
A circuit that is capable of adding or subtracting binary numbers.
adder-subtractor: one circuit, two arithmetic modes
An adder-subtractor is a single digital logic circuit that performs both addition and subtraction of binary numbers under the control of a mode signal. The same hardware executes either operation without reconfiguration, switching between them via a control input that typically selects whether the circuit adds or subtracts on each clock cycle or combinational pass.
The circuit exploits the two's complement representation of negative numbers. To subtract B from A, the adder-subtractor inverts all bits of B (forming one's complement) and adds 1, then performs standard binary addition with A. A control line gates this inversion and carry-in operation; when the mode bit is 0, the circuit adds directly; when set to 1, it inverts B and forces an initial carry, effectively computing A minus B. This unified approach eliminates the need for separate adder and subtractor blocks.
Implementation typically uses a chain of full adders, where XOR gates at each bit stage conditionally flip the B input based on the mode control. The first XOR also receives the control signal as a carry-in. An N-bit adder-subtractor requires N full adders, N XOR gates, and minimal additional logic, making it more economical than duplicating arithmetic units. Propagation delay grows with bit width because carries ripple through each stage.
Adder-subtractors appear in processor arithmetic logic units (ALUs), microcontrollers, and signal processing pipelines wherever both operations are needed. They are fundamental to any system performing signed arithmetic. Modern designs often cascade faster adder variants, such as carry-lookahead or Kogge-Stone structures, to reduce delay and power consumption in wider datapaths.
A common limitation is carry propagation time in ripple-carry designs, which becomes critical above 16 or 32 bits. Overflow detection is also required when working with fixed-width integers; the circuit must flag when results exceed the representable range. These constraints drive the choice between simple ripple implementations and more complex but faster carry-skip or prefix adder topologies in production designs.