fanout

In digital logic and electronics, fanout is the number of logic gate inputs that a single output can safely supply with current while maintaining valid signal levels. A gate output rated for a fanout of 10 can reliably drive 10 standard logic inputs without degrading the output voltage or exceeding the source current limit. Exceed that number and the output voltage sags, logic levels become unreliable, and the circuit fails intermittently.

Fanout depends on two electrical realities: the amount of current the output stage can source or sink, and the input current each downstream gate demands. Older TTL logic typically had fanout of 10 to 20; modern CMOS outputs can drive 50 or more because they draw almost no input current. When you chain multiple gates or drive transmission line terminations, parallel resistors, or large capacitive loads, the current demand rises and effective fanout shrinks. A designer must track this budget as carefully as power consumption.

Fanout in practice and pitfalls

The term also appears in physical design: a signal line from a clock generator or reset source that fans out across a chip or board branches into many parallel traces or through a buffer tree. Each branch is still counted in the fanout specification. Violating fanout ratings causes slow rise times, overshoot, reflections, and metastability in flip-flops.

In high-speed circuits, fanout interacts with slew rate, impedance, and capacitive loading. A logic output capable of driving 100 inputs at DC may fail at 100 MHz because the parasitic capacitance of 100 gate inputs creates too much load capacitance; the slew rate constraint is hit first. Designers combat this with buffers, repeaters, or active fanout trees that regenerate the signal.

The word itself is mechanical in origin, borrowed from how a shaft splits into multiple driven elements. In electronics it has become almost purely an electrical measure, but the mental model holds: one source, many destinations, limited by the bandwidth of the connection.