gate array

A gate array is a prefabricated silicon wafer containing thousands of identical logic gates and transistors arranged in a regular grid pattern, with no interconnections between them. The manufacturer produces these chips in volume; you then define what the array actually does by specifying how those gates should be wired together. This two-stage manufacturing process sits between buying a standard off-the-shelf logic chip and commissioning a fully custom integrated circuit from scratch.

The typical gate array starts as a base layer of transistors, usually NAND or NOR gates, deposited across the die in rows and columns. Metal layers above this grid remain unconnected. When you send your design to the foundry, they add custom metal routing on the top layers only, connecting your gates in the pattern your circuit requires. This selective metallization means the expensive, time-consuming early fabrication steps have already happened in volume, reducing your non-recurring engineering costs compared to full custom design.

Density and speed trade-offs

Gate arrays sacrifice some efficiency for speed to market. Because the underlying transistor layout is fixed, you cannot optimize every corner of the design as you could with a custom chip. This means gate arrays typically use more die area than an equivalent fully custom circuit and consume more power. However, they are far faster and cheaper to produce than custom silicon, with turnaround measured in weeks rather than months. Gate arrays have been largely displaced by field-programmable gate arrays (FPGAs) for small production runs, since FPGAs require no foundry step at all, but gate arrays remain common where volume justifies the minimal setup cost and where the performance or power characteristics demand real silicon over FPGA alternatives.

Gate array design requires a hardware description language (HDL) or detailed schematic to specify which gates connect to which, and how signals flow through the array. Design rule checks and layout verification must confirm that your routing fits within the metal layers and respects design rules for that technology node. A single metallization step can contain mistakes that are expensive to fix, so simulation and verification are rigorous before sending masks to the foundry.

The term gate array reflects the orthogonal structure of the underlying transistor layout: an array of gate elements awaiting metallization. This architecture emerged in the 1970s as a compromise between the long lead times of custom chips and the limited functionality of standard off-the-shelf ICs. Though less common now, gate arrays remain relevant in applications requiring moderate volume production where lead time and cost matter more than maximum density.