half adder

A half adder is a logic circuit that adds two single binary digits and produces a sum bit and a carry bit as outputs. It takes two input bits, conventionally called A and B, and generates two outputs: the sum (S) and the carry (C). The sum output is 1 when the inputs are different; the carry output is 1 only when both inputs are 1. This is the simplest form of binary addition at the circuit level.

The half adder uses two gates: an XOR gate produces the sum bit, while an AND gate produces the carry bit. When built from discrete logic, it occupies minimal board space and draws negligible power. In modern practice, half adders appear rarely as standalone components; instead, they serve as the theoretical foundation for understanding binary arithmetic in digital systems and appear as building blocks within larger arithmetic circuits like adders and arithmetic logic units.

Why it is called a half adder

The term derives from its limitation: it cannot accept a carry input from a previous addition stage. A full adder, by contrast, handles three inputs (the two bits plus an incoming carry) and can therefore chain together to add multi-bit numbers. The half adder performs only half the job needed for practical multi-bit addition, hence the name. In cascaded arithmetic, you typically use a half adder only for the least significant bit position, then full adders for all higher positions.

Half adders appear in educational contexts and in the design documentation of processors and custom logic circuits, where they illustrate how elementary logical operations combine to perform computation. They also show up in certain specialized signal processing or modulo-arithmetic circuits where two-bit addition without carry propagation is sufficient. Understanding the half adder is essential for anyone learning digital logic design or working on low-level hardware verification.