jitter

Jitter is the short-term, seemingly random deviation of a signal's timing from its ideal position. In a digital clock signal, it means the rising and falling edges don't arrive exactly when they should. In an analog signal, it manifests as noise modulation. The core problem is the same: unpredictable time-domain variations that degrade signal quality and wreak havoc on synchronization, data recovery, and measurement accuracy.

In digital circuits, jitter typically gets measured in picoseconds or nanoseconds. A clock signal that should transition at exactly 1 nanosecond intervals might drift by tens or hundreds of picoseconds on either side of that ideal time. This matters hugely because high-speed data receivers use clock edges as timing references; jitter directly translates to uncertain sampling windows and bit errors. In practical terms, a 10 GHz serial link with jitter greater than a few dozen picoseconds becomes unreliable.

Jitter comes from multiple physical origins. Power supply noise couples into oscillator circuits and clock distribution trees, causing frequency modulation. Thermal drift in components changes propagation delays. Cross-talk from adjacent signal lines induces time-domain coupling. Phase-locked loops (PLLs) that generate clocks have inherent jitter related to their loop bandwidth and reference source quality. Ground plane discontinuities and impedance mismatches on transmission lines create reflections that blur edge timing. In fiber-optic systems, chromatic dispersion and mode-partition noise introduce jitter.

Engineers distinguish between deterministic jitter, which has a repeating or predictable pattern tied to signal events (like data-dependent jitter or periodic supply ripple), and random jitter, which follows statistical distributions. The total jitter budget on a high-speed link must account for both. Practical measurement uses oscilloscopes with statistical analysis, eye diagrams, or dedicated jitter analyzers that separate components and characterize their probability distributions.

Mitigation strategies depend on the jitter source. Clock distribution often requires low-skew buffers, careful PCB layout with controlled impedance and isolated power planes, and sometimes on-chip PLL de-jittering. Receiver-side solutions include adaptive equalization, DLL (delay-locked loop) frequency synthesis, and jitter-tolerant deserializers. For analog signals, low-phase-noise oscillators and low-noise power supplies reduce jitter at the source. The term itself likely derives from the jerky, jittery appearance of a signal's edges on an oscilloscope display when jitter is pronounced.