latch-up

Latch-up is a destructive failure mode in CMOS and other semiconductor circuits where a parasitic thyristor structure activates and creates a low-impedance path directly from the positive power rail to ground. Once triggered, this path sustains itself and draws enormous current, usually measured in amps, until the power supply is disconnected or the current limit is exceeded. The circuit essentially latches into a shorted state, which is where the name comes from.

The parasitic structure exists in the substrate of every CMOS die. An N-channel MOSFET has a P-type body region, and beneath it lies an N-well. A P-channel device occupies the N-well. These form the collector and base of unwanted vertical and lateral bipolar transistors. Under normal conditions these transistors remain off. But if either the N-well or the P-substrate sees a voltage spike or excessive current injection, one transistor turns on, which causes the other to turn on, creating positive feedback and the thyristor action.

Common triggers include electrostatic discharge (ESD) that exceeds the chip's input protection, overvoltage on any pin, or high di/dt (rapid current changes) in the power supply leads. The voltage must swing far enough to forward-bias the parasitic junctions. Once latch-up begins, the impedance drops so sharply that the circuit current can exceed the package bond wire limits within microseconds, melting internal metal connections or causing wire fusing and permanent damage.

Design and protection measures

Modern chip design combats latch-up through several techniques: guard rings of doped material isolate N-wells and P-substrates to prevent parasitic current paths; well bias contacts ensure the substrate and wells are held at safe potentials; and reduced spacing between transistors limits where parasitic components can form. Process nodes below 0.5 micrometers are inherently safer due to smaller junction depths and lower impedances. On the board level, careful power distribution, series source impedance, and low-inductance paths reduce the voltage swings that trigger the effect.

Testing for latch-up susceptibility is mandatory in CMOS design validation. Standards such as JEDEC JS-001 define ESD test methods and latch-up immunity requirements. Failure analysis of a latch-up failure typically shows a small melted region on the die, often near I/O pads where protection is concentrated. Industrial and automotive applications require particular attention to latch-up margins because the circuits operate in harsh electrical environments and cannot tolerate field failures.