pMOS
a MOSFET with a p-type channel (a semiconductor doped with an element creating a surplus of holes).
pMOS: the MOSFET that conducts via holes, not electrons
A pMOS transistor is a metal-oxide-semiconductor field-effect transistor built on an n-type substrate with a p-type inversion layer as its conducting channel. Current flows through holes (positive charge carriers) rather than electrons. The device switches or amplifies by applying a negative voltage to the gate relative to the source, which attracts holes into the channel and reduces the potential barrier. When gate voltage reaches threshold, roughly -0.4 to -0.7 volts depending on the process node, the channel conducts.
pMOS transistors are slower than their nMOS counterparts because hole mobility in silicon is about 2.5 times lower than electron mobility. This tradeoff is accepted because pMOS devices excel at pulling signal lines to the positive supply voltage (VDD), complementing nMOS devices that pull toward ground. In complementary MOS (CMOS) logic, the pairing of pMOS and nMOS in push-pull configuration eliminates steady-state current draw, making CMOS the dominant logic family since the 1980s.
Common failure modes and practical constraints
Electromigration and hot-carrier effects affect pMOS less severely than nMOS at the same geometry, but thermal effects still dominate modern reliability concerns. Gate oxide degradation under negative gate-source voltage stress remains a design consideration. In analog circuits, pMOS devices are preferred as current sources and active loads because their high output impedance and gate controlled current make them suitable for gain stages. The slow switching speed limits pMOS to applications where speed is not the bottleneck, such as biasing networks or high-impedance current mirrors.
The "p" designation refers purely to the channel doping type, distinguishing pMOS clearly from nMOS in schematic notation and datasheet tables. Modern process nodes down to 5 nanometers still use pMOS transistors in the logic libraries, though the distinction between p-type and n-type dopants becomes less intuitive as gate-length scaling approaches physical limits. Layout rules for pMOS emphasize source and bulk connection to VDD and require careful attention to parasitic diode conduction paths if substrate voltage swings occur unexpectedly.