pMOSFET
A type of metal, oxide, semiconductor field-effect transistor (MOSFET) that utilizes an p-type channel, conducting when a voltage voltage below a threshold is applied to the gate relative to the source. It is commonly used in complementary metal, oxide, semiconductor (CMOS) technology alongside nMOSFETs.
pMOSFET: the positive-channel switch in every modern chip
A pMOSFET is a field-effect transistor built on a p-type (positive) semiconductor channel, typically sitting on an n-type substrate. When you apply a negative voltage to its gate relative to its source, the device turns on and allows current to flow from source to drain. It is the complement to the nMOSFET, and together they form the foundation of CMOS logic, the standard technology in microprocessors, memory, and digital circuits for the past four decades.
The name comes from its doped channel: a p-type channel is created by doping with acceptor impurities such as boron in a silicon substrate. When the gate voltage drops sufficiently below the source voltage, holes accumulate at the oxide interface, forming a conductive path. The threshold voltage (Vt) for a pMOSFET is typically negative, ranging from around -0.3 V to -0.7 V depending on process technology and device design.
Why pMOSFETs matter in CMOS
CMOS circuits use pMOSFETs as the pull-up network and nMOSFETs as the pull-down network. This dual-transistor design consumes almost no static power, because one device is always off. A pMOSFET pulls the output high when needed; an nMOSFET pulls it low. This complementary arrangement is why supply voltage scaling and power efficiency have driven semiconductor technology for decades.
Practical trade-offs arise from physics: pMOSFETs have lower carrier mobility (hole mobility in silicon is roughly half electron mobility) than nMOSFETs, so they conduct less current for the same gate length and oxide thickness. To maintain balanced switching speed in a CMOS gate, pMOSFETs are typically made 2 to 3 times wider than their nMOSFET pairs, consuming extra chip area and capacitance.
In modern process nodes (below 28 nm), pMOSFETs face additional challenges: strain engineering, which boosts nMOSFET speed, offers smaller gains for pMOSFETs; leakage current becomes harder to control; and the gate oxide thickness must shrink to maintain controllability, pushing devices closer to quantum tunneling limits. Designers compensate through multiple Vt variants, threshold voltage tuning, and sometimes different channel orientations or fin structures in FinFET and GAA designs.