TLB

A translation lookaside buffer is a small, fast cache that sits inside or very close to a processor core and stores recent virtual-to-physical memory address translations. When software running on a CPU requests data at a virtual memory address, the MMU (memory management unit) must normally consult the page table in RAM to find the corresponding physical address. This lookup is slow. The TLB intercepts these requests and returns a cached translation in a single cycle if the address pair has been used recently, bypassing the page table entirely.

TLB capacity is measured in entries, typically ranging from 16 to 512 depending on the processor design and cache level. A modern x86-64 CPU might have separate instruction and data TLBs, each with multiple levels: an L1 TLB that is tiny and very fast, and an L2 TLB that is larger but slightly slower. When a virtual address is not found in the TLB, a TLB miss occurs and the processor must walk the page table, a costly operation that can stall execution for hundreds of cycles.

Performance and system behavior

TLB efficiency becomes critical in workloads that touch large memory regions or have poor locality. A process scanning gigabytes of data may experience frequent misses if the page size is fixed (commonly 4 kB on Linux x86) and the TLB cannot hold translations for the working set. Many systems now support multiple page sizes: in addition to 4 kB pages, 2 MB or 1 GB huge pages reduce the number of translations needed, though they consume more memory and are harder to manage.

When a process context switch occurs, the TLB typically becomes stale because the virtual addresses of the new process map to different physical memory. Most modern CPUs tag TLB entries with a process identifier (ASID or process context ID) to avoid full flushes, though some older systems must clear the entire TLB on every switch. Utility professionals optimizing real-time control systems or high-frequency trading engines often profile TLB miss rates using performance counters and tune page size allocation and process affinity to maximize cache hit rates.

The term lookaside buffer reflects the architecture: the TLB sits to the side of the main execution path, consulted in parallel with other address translation logic. It is one of several invisible but performance-critical structures that separate perceived memory speed from actual RAM latency, alongside L1, L2, and L3 instruction and data caches.