elaboration
The process of taking a parsed tree of an abstract integrated circuit definition in a language such as Verilog and creating a hierarchy of module instances that ends with primitive (atomic) gates and statements.
elaboration: turning design code into a gate-level circuit
Elaboration is the intermediate compilation stage in hardware design where a behavioral or structural description written in Verilog, VHDL, or similar languages gets transformed into an explicit hierarchy of circuit components. It takes your high-level design code and unrolls it into a tree of instantiated modules, parameters, and primitive gates that a synthesis tool or simulator can actually work with. Without elaboration, the design file remains abstract; elaboration makes it concrete.
The process begins with parsing the source code into an abstract syntax tree. Then the elaborator recursively expands module instantiations, resolves parameters, generates array instances, and flattens or preserves hierarchy according to compiler directives. Generate blocks are unrolled, conditional compilation (ifdef) blocks are evaluated, and port connections are resolved. The result is a fully elaborated design tree where every signal, port, and gate has a definite identity and location in the module hierarchy.
Elaboration in simulation and synthesis
Elaboration happens early in both the simulation and synthesis flows but produces slightly different outputs depending on the tool. A simulator elaborates the design to prepare it for behavioral execution, preserving procedural blocks and maintaining timing annotations. A synthesis tool elaborates the design to prepare it for optimization and technology mapping, potentially flattening the hierarchy or handling special constructs like memories differently. Elaboration errors, such as mismatched port widths or undefined module references, typically halt the entire flow.
Common elaboration problems include parameter mismatches in nested module instantiations, unresolved generate blocks when conditional logic depends on runtime values, and clock domain crossings that appear only after elaboration reveals the actual interconnect. Large designs with deep module hierarchies or extensive parameter sweeping can produce very large elaborated trees that consume significant memory during synthesis.
The name reflects the sense of expanding something simple into something detailed and fully worked out, borrowed from general English usage. In the VLSI design world, elaboration sits between human-readable design entry and machine-executable synthesis, making it the essential bridge that no digital design flow can skip.