parasitic

A parasitic is an electrical property or component present in a real circuit but absent from its schematic diagram. It arises from the physical reality of conductors, insulators, and geometry; when you draw a wire as a simple line, you are ignoring its actual resistance, inductance, and capacitance. When you draw a transistor, you are ignoring the capacitance between its leads and substrate. These ignored properties often matter enormously at high frequency, high current, or high speed, where they degrade performance, introduce noise, cause crosstalk, or trigger oscillation.

The three main parasitic families are resistance, inductance, and capacitance. Parasitic resistance appears in interconnect, bond wires, and via structures; it dissipates power and raises noise floor. Parasitic inductance, measured in nanohenries per millimeter of conductor length, is the dominant problem in switching power supplies and high-speed digital circuits; it causes voltage overshoot, ringing, and electromagnetic interference. Parasitic capacitance appears between any two conductors separated by dielectric, including adjacent traces on a PCB, leads of a component, and regions of a silicon die. At low frequency it is invisible; at gigahertz frequencies it couples signals, loads amplifier output, and dominates impedance.

Extraction and management

Modern integrated circuit design includes parasitic extraction, a computational step that simulates the actual geometry of the layout, calculates all parasitic elements numerically, and updates the circuit model before simulation. The extracted netlist includes resistances (milliohms to ohms), inductances (picohenries to nanohenries), and capacitances (femtofarads to picofarads) attached to every node. Without extraction, simulation predicts behavior that the fabricated chip will not exhibit.

In board-level design, parasitic management begins with layer stackup, trace routing, and via placement. A power distribution network with poor inductance will ring when the load switches; a differential pair with uncontrolled spacing and routing will couple crosstalk into neighboring signals. Measurement tools such as vector network analyzers and time-domain reflectometry reveal parasitic effects in assembled boards. High-speed designers routinely simulate the frequency response of interconnect, calculate insertion loss, and model stub effects from unterminated vias.

The term parasitic is borrowed from biology: like a parasite, these effects do not appear in the idealized schematic but feed on the energy and bandwidth of the circuit, degrading its intended function. Ignoring parasitic effects is a common source of failure in designs that work in simulation but fail on the bench.