positive-edge-triggered

A positive-edge-triggered circuit responds to the transition of a signal from low to high, technically called the rising edge. This happens at a specific instant, typically within nanoseconds of the voltage crossing the threshold between logic 0 and logic 1. The circuit ignores the signal's value before that moment and after it; only the crossing itself matters. This behavior is foundational to digital timing and synchronization.

The most common positive-edge-triggered device is the D flip-flop, used in counters, shift registers, and state machines. When the clock input rises, the flip-flop captures whatever voltage sits on its data input and holds that value until the next rising edge. Microcontrollers and digital signal processors use positive-edge-triggered logic on their input capture pins to timestamp external events. Timing is tight: propagation delay from the rising edge to a valid output state is measured in tens to hundreds of picoseconds on modern silicon.

The alternative is negative-edge-triggered, which responds when the signal falls from high to low. Some circuits require both edges; these are called edge-sensitive or dual-edge-triggered. The choice affects the timing relationships in a larger circuit and must be coordinated carefully. Mixing triggered behaviors in the same circuit creates metastability risk if signal edges are not properly separated in time.

The term derives from terminology in digital logic where a signal's 'edge' is the rapid voltage transition. 'Positive' refers to the upward direction of that transition, as opposed to 'negative' (downward). This naming is independent of whether the signal represents a high or low state electrically; it refers only to the direction of change. In schematic diagrams, positive-edge-triggered inputs are marked with a small triangle at the clock port, pointing upward.

Detection of the rising edge requires a mechanism inside the chip: typically a one-shot circuit or cross-coupled gates that respond only to the transition interval, not the static level. Noise near the threshold can cause false triggering, so industrial designs often add hysteresis or Schmitt-trigger buffers on input lines before they reach the triggered element. Timing specifications like setup time (how long the data must be stable before the edge) and hold time (how long after the edge) are critical to reliable operation.