programmable logic array

A programmable logic array (PLA) is a semiconductor device that implements combinational logic by routing electrical signals through a grid of fused or programmed connections. Unlike a fixed logic chip designed for one specific function, a PLA allows you to configure its internal pathways after manufacturing to perform your chosen logic operations. The basic structure consists of an AND plane followed by an OR plane, where each intersection can be selectively enabled or disabled to build sum-of-products Boolean expressions.

PLAs typically contain 10 to 100 inputs and outputs, though variations exist. Each input line fans across the AND plane, where multiple inputs can be combined via AND gates. The outputs of those AND gates then feed into the OR plane, where outputs are formed by ORing selected AND results together. Configuration happens during programming, which may use fuses (one-time programmable), antifuses, floating-gate transistors, or SRAM cells depending on the device type. Early PLAs from the 1970s and 1980s used bipolar fuse technology and required specialized programming equipment; modern variants often use SRAM or flash-based approaches.

The trade-off of a PLA versus a generic microprocessor or field-programmable gate array (FPGA) reflects its narrower scope. A PLA excels at pure combinational logic without sequential state, making it lightweight and deterministic. It consumes less power than a full programmable device and requires no clock signal. However, it cannot implement sequential circuits, memory, or complex arithmetic without external components. This makes PLAs suitable for decoder networks, address translation, state encoding, and control signal generation in mid-range industrial applications.

Practical use and limitations

In practice, PLAs are most useful when you have a fixed set of inputs mapping to a fixed set of outputs, with no need for feedback or state memory. A classic example is converting a binary-coded address into chip-select signals, or implementing priority encoding for interrupt handling. They integrate directly into larger boards without additional logic chips, reducing component count and power draw. However, if your logic becomes complex enough that you exhaust the AND plane capacity, you must cascade multiple PLAs or switch to an FPGA, which is more flexible but larger and slower to implement.

The term "array" reflects the grid structure of programmable cells; "logic array" distinguishes it from memory arrays. Modern use of PLAs has declined as FPGAs have become cheaper and more accessible, though PLAs remain embedded in some microcontrollers and application-specific integrated circuits (ASICs) for low-overhead logic synthesis. When selecting between a PLA, PAL (programmable array logic, which has fixed OR plane), and FPGA, consider your logic depth, power budget, and whether sequential behavior matters.