Steiner point

A Steiner point is an additional vertex introduced into a network routing problem to reduce total wire length below what a direct tree connecting only the required terminals would achieve. In printed circuit board design and interconnect routing, the goal is to connect a set of fixed nodes (component pins, vias, or signal points) with the shortest possible total conductor length. A Steiner point is not one of these required terminals; rather, it is a new junction point placed at an optimal location where multiple conductor segments meet, allowing the routing to bend and split in ways that save distance overall.

The concept originates from Fermat point geometry but takes its name from Jakob Steiner's work on minimal networks. In the plane, a Steiner point where three conductor segments meet creates 120-degree angles at optimality, a property that drives physical layout algorithms. For a simple two-point connection, no Steiner point helps; for three or more points, adding one or more Steiner points can reduce total length by 10 to 15 percent in typical cases. The maximum theoretical saving across all configurations approaches 13.4 percent when optimal Steiner trees replace minimum spanning trees.

Practical use in routing and design

In electronic design, Steiner points appear most often in clock tree synthesis, power distribution networks, and signal routing on large chips or high-speed boards. A router software package computes candidate Steiner point locations to join nets of three or more terminals. Each added Steiner point increases routing complexity and requires careful placement to avoid introducing crosstalk or capacitive coupling. In some design flows, Steiner points are placed on a rectilinear grid (Manhattan geometry) rather than freely in the plane, which simplifies manufacturing but reduces the distance benefit.

The Steiner tree problem itself is NP-hard, meaning no known polynomial-time algorithm solves it exactly for large graphs. Practical routing tools use heuristics and approximation algorithms, such as Iterated 1-Steiner or Batched Steiner techniques, that run in acceptable time on real netlists with thousands or millions of nodes. The tradeoff between solution quality and compute time is central to design tool performance at advanced technology nodes.

Steiner points must be distinguished from intermediate routing segments that cross or change direction without branching. A true Steiner point is a junction where the network topology changes; collapsing or removing it would alter which terminals are directly connected. In congested areas of a chip or board, Steiner points may be sacrificed or moved slightly to meet routing resource constraints, accepting a small length penalty for physical feasibility.